NextSilicon’s Maverick-2 locks onto bottleneck code

• NextSilicon has developed a novel chip that adapts its hardware to accelerate high-performance computing applications.
• The Maverick-2 is claimed to have up to 4x the processing performance per watt of graphics processing units (GPUs) and 20x that of high-performance general processors (CPUs).

After years of work, the start-up NextSilicon has detailed its Maverick-2, what it claims is a new class of accelerator chip.

Brandon Draeger

A key complement to the chip is NextSilicon’s software, which parses the high-performance computing application before mapping it onto the Maverick-2. 

“CPUs and GPUs treat all the code equally,” says Brandon Draeger, vice president of marketing at NextSilicon. “Our approach looks at the most important, critical part of the high-performance computing application and we focus on accelerating that.”

With the unveiling of the Maverick-2 NextSilicon has exited its secrecy period.

Founded in 2017, the start-up has raised $303 million in funding and has 300 staff.  The company is opening two design centres—in Serbia and Switzerland—with a third planned for India. The bulk of the company’s staff is located in Israel.

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The computing problem of our time: Moving data

• Celestial AI's Photonic Fabric technology can deliver up to 700 terabits per second of bidirectional bandwidth per chip package.
• The start-up has recently raised $100 million in funding.

The size of AI models that implement machine learning continue to grow staggeringly fast.

Such AI models are used for computer vision, large language models such as ChatGPT, and recommendation systems that rank items such as search results and music playlists.

David Lazovsky

The workhorse silicon used to build such AI models are graphics processing units (GPUs). GPU processing performance and their memory size may be advancing impressively but AI model growth is far outpacing their processing and input-output [I/O] capabilities.

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Broadcom's first Jericho3 takes on AI's networking challenge

Broadcom’s Jericho silicon has taken an exciting turn.

Oozie Parizer

The Jericho devices are used for edge and core routers.

But the first chip of Broadcom’s next-generation Jericho is aimed at artificial intelligence (AI); another indicator, if one is needed, of AI’s predominance.

Dubbed the Jericho3-AI, the device networks AI accelerator chips that run massive machine-learning workloads.

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Ayar Labs gets to work with leading AI and HPC vendors

Optical interconnect specialist Ayar Labs has announced that it is working with Nvidia, a leader in artificial intelligence (AI) and machine learning silicon, systems and software.

In February Ayar Labs announced a strategic collaboration with the world’s leading high-performance computing (HPC) firm, Hewlett Packard Enterprise (HPE).

Charles Wuischpard

Both Nvidia and HPE were part of the Series C funding worth $130 million that Ayar Labs secured in April.

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Nvidia's plans for the data processor unit

When Nvidia’s CEO, Jensen Huang, discussed its latest 400-gigabit BlueField-3 data processing unit (DPU) at the company’s 2021 GTC event, he also detailed its successor.

Companies rarely discuss chip specifications two generations ahead; the BlueField-3 only begins sampling next quarter.

BlueField-3 die. Source: Nvidia

The BlueField-4 will advance Nvidia’s DPU family. It will double again the traffic throughput to 800 gigabits-per-second (Gbps) and almost quadruple the BlueField-3’s integer processing performance.

But one metric cited stood out. The BlueField-4 will increase by nearly 1000x the number of terabit operators-per-second (TOPS) performed: 1,000 TOPS compared to the BlueField-3’s 1.5 TOPS.

Huang said artificial intelligence (AI) technologies will be added to the BlueField-4, implying that the massively parallel hardware used for Nvidia’s graphics processor units (GPUs) are to be grafted onto its next-but-one DPU.

Why add AI acceleration? And will it change the DPU, a relatively new processor class?

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Intel sets a course for scalable optical input-output

• Intel is working with several universities to create building-block circuits to address its optical input-output (I/O) needs for the next decade-plus.

• By 2024 the company wants to demonstrate the technologies achieving 4 terabits-per-second (Tbps) over a fibre at 0.25 picojoules-per-bit (pJ/b).

Intel has teamed up with seven universities to address the optical I/0 needs for several generations of upcoming products.

The initiative, dubbed the Intel Research Center for Integrated Photonics for Data Centre Interconnects, began six months ago and is a three-year project.

No new location is involved, rather the research centre is virtual with Intel funding the research. By setting up the centre, Intel’s goal is to foster collaboration between the research groups.

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Ayar Labs prepares for the era of co-packaged optics

The first of two articles on co-packaged optics.

Part 1: Ayar Labs

Ayar Labs is readying its co-packaged optics technology for scaled production in the second half of 2020. So says CEO Charlie Wuischpard who joined the start-up in late 2018 after it secured $24 million in funding to bring its products to market.

Co-packaged optics refers to the intimate coupling of optics with an ASIC in one package. Such tightly-coupled optics promises to overcome the growing system challenges associated with linking an ASIC’s high-speed signals to pluggable optics residing on a platform’s faceplate.

Charlie Wuischpard Wuischpard joined Ayar Labs from Intel where he led the supercomputing segment within the company’s data centre group. Wuischpard also led Intel’s disaggregated rack initiative.

“In both these, silicon photonics plays a huge role in enabling future architectures and future designs,” he says.

Ayar Labs raised its funding after demonstrating successfully its optical designs: a silicon-photonics optical chiplet, dubbed Teraphy, and its Supernova external laser source. 

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