Packaging silicon photonics using passive alignment

• An Israeli start-up is tackling a key packaging challenge for silicon photonics

Teramount has developed a way to simplify the packaging of silicon photonics chips. Instead of using active alignment whereby an external laser is required to carefully align a fibre to the optical die, the Israeli start-up has developed a technology that allows passive alignment.  

Hesham Taha“If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging,” says Hesham Taha, Teramount's CEO.

Taha worked at a company developing atomic force microscopy systems before co-founding Teramount. "We got to know of the problem of injecting light into a waveguide and were surprised that the industry was still using active alignment," he says.

This spurred Taha and a colleague to develop optical solutions to match a single-mode fibre core to an optical waveguide, and they founded Teramount in Jerusalem in 2013. "We started real activity at the beginning of 2015 after getting funding," says Taha.

Existing silicon photonics companies either develop their own customised active alignment equipment or outsource the activity to a third party. "If we solve one of the bottlenecks of silicon photonics in terms of packaging, silicon photonics will be more and more adopted," says Taha.

If we want silicon photonics to ramp up to volume, it has to meet CMOS standards both in terms of fabrication and packaging

The design

Teramount's solution includes two elements: a PhotonicsPlug that is flip-chipped onto the silicon photonics die while still part of a wafer, and a 'bump', a design element added on the silicon photonics chip next to the optical waveguide. "Our solution, which we will be selling, is the PhotonicsPlug and we do require them [the designers] to add one element [the bump] to their silicon photonics chip," says Taha. 

The main PhotonicsPlug component is a silicon die comprising optics that manipulates the beam using self-aligning optics and focusses it onto the silicon photonics chip via a glass spacer. Teramount’s die also has V-grooves to interface the single-mode ribbon fibre. Teramount says its die is made using an inexpensive mature CMOS process due to the relatively large feature sizes of the optical elements.

The second design element - the bump - is added next to the silicon photonics chip's grating coupler. The grating coupler is one of two techniques used in the industry to interface a fibre to the waveguide, the other being edge coupling.

“We want to place it [the bump] next to the waveguide so that the optics of the PhotonicPlug works in conjunction with it so that it brings the beam to the waveguide with a large tolerance,” says Taha. The bump is accurately placed on the chip using standard lithography techniques.

The resulting tolerance with which the die can be attached to the silicon photonics wafer is up to ± 20 microns in each of the three dimensions such that standard flip-chip machines can attach the PhotonicsPlug to the wafer. 

“Flip-chip machines today work with a tolerance of ± 6 microns and can do 1,500 assemblies per hour,” says Taha.

"This is the main philosophy we are bringing here," he says. "Instead of the accurate placement of the fibre next to the grating coupler which requires active alignment, we want to replace that with a cheaper alignment technique that has much better accuracy at the wafer level," says Taha.

Status

Teramount has already shown working devices using the technology. In addition, Teramount is working with several partners and has demonstrated its technology with their silicon photonics chip designs. "With these partners we are doing the integration and qualifying the performance of the device," says Taha. "We will finalise at least two of these partnerships within a few months."

The start-up is also working to enable volume manufacturing by bringing its technology to industrial fabrication plants. This will be completed in the next few months.

Being a small start-up, the company is focussed on developing the grating coupler solution but it has already started work on an edge-coupling technique to a device’s waveguides. Edge coupling is suited to wavelength-division multiplexing (WDM) silicon photonics chips. That is because grating couplers are wavelength-dependent while edge coupling supports a broader range of wavelengths.