OIF adds a short-reach design to its 1600ZR/ ZR+ portfolio

The OIF (Optical Internetworking Forum) has broadened its 1600-gigabit coherent optics specification work to include a third project, complementing the 1600ZR and 1600ZR+ initiatives.

Karl Gass

The latest project will add a short-reach 'coherent-lite' digital design to deliver a reach of 2km to 20km and possibly 40km with a low latency below 300ns.

The low latency will suit workloads and computing resources distributed across data centres.

"The coherent-lite is more than just the LR (long reach) work that we have done [at 400 gigabits and 800 gigabits]," says Karl Gass, optical vice chair of the OIF's physical link layer (PLL) working group, adding that the 1600-gigabit coherent-lite will be a distinct digital design.

Doubling the data rate from 800 gigabits to 1600 gigabits is the latest battle line between direct-detect and coherent pluggable optics for reaches of 2km to 40km.

At 800 gigabits, the OIF members debated whether the same coherent digital signal processor would implement 800ZR and 800-gigabit LR. Certain OIF members argued that unless a distinct, coherent DSP is developed, a coherent optics design will never be able to compete with direct-detect LR optics.

"We have that same acknowledgement that unless it's a specific design for [1600 gigabit] coherent-lite, then it's not going to compete with the direct detect," says Gass.

OIF's 1600-gigabit specification work

The OIF's 1600-gigabit roadmap has evolved rapidly in the last year.

In September 2023, the OIF announced the 1600ZR project to develop 1.6-terabit coherent optics with a reach of 80km to 120km. In January 2024, the OIF announced it would undertake a 1600ZR+ specification, an enhanced version of 1600ZR with a reach of 1,000km.

The OIF's taking the lead in ZR+ specification work is a significant shift in the industry, promising industry-wide interoperability compared to the previous 400ZR+ and 800ZR+ developments.

Now, the OIF has started a third 1600-gigabit coherent-lite design.

1600ZR development status

Work remains to complete the 1600ZR Implementation Agreement, the OIF's specification document. However, member companies have agreed upon the main elements, such as the framing schemes for the client side and the digital signal processing and using oFEC as the forward error correction scheme.

oFEC is a robust forward error correction scheme but adds to the link's latency. It has also been chosen as the forward error correction scheme for 1600ZR. The OIF members want the 'coherent-lite' version to use a less powerful forward error correction to achieve lower latency.

The 1600ZR symbol rate chosen is around 235 gigabaud (GBd), while the modulation scheme is 16-ary quadrature amplitude modulation (16-QAM). The specified reach will be 80km to 120km. (See table below.)

The members will likely agree on the digital issues this quarter before starting the optical specification work. Before completing the Implementation Agreement, members must also spell out interoperability testing.

1600ZR+ development status

The 1600ZR+ work still has some open questions.

One is whether members choose a single carrier, two sub-carriers, or four to achieve the 1,000km reach. The issue is equalisation-enhanced phase noise (EEPN), which imposes tighter constraints on the received laser. Using sub-carriers, the laser constraints can be relaxed, enabling more suppliers. The single-carrier camp argues that sub-carriers complicate the design of the coherent digital signal processor (DSP).

The workgroup members have also to choose the probabilistic constellation shaping to use. Probabilistic constellation shaping gain can extend the reach, but it can also reduce the symbol rate and, hence, the bandwidth specification of the coherent modem's components.

The symbol rate of the 1600ZR+ is targeted in the range of 247GBd to 263GBd.

Power consumption

The 1600ZR design's power consumption was hoped to be 26W, but it is now expected to be 30W or more. The 1600ZR+ is expected to be even higher.

The coherent pluggable's power consumption will depend on the CMOS process that the coherent DSP developers choose for their 1600ZR and 1600ZR+ ASIC designs. Will they choose the state-of-the-art 3nm CMOS process or wait for 2nm or even 1.8nm to become available to gain a design advantage?

Timescales

The target remains to complete the 1600ZR Implementation Agreement document quickly. Gass says the 1600ZR and 1600ZR+ Implementation Agreements could be completed this year, paving the way for the first 1600ZR/ZR+ products in 2026.

"We are being pushed by customers, which isn't a bad thing," says Gass.

The coherent-lite design will be completed later given that it has only just started. At present, the OIF will specify the digital design and not the associated optics, but this may change, says Gass.