Acacia Communications has revealed the innards of its 100 Gig coherent pluggable module for metro networks. The AC-100 CFP combines a low-power DSP-ASIC with a silicon-photonics-based optics chip. The CFP's reach is 80km to 1,200km, and its power consumption is 24-26W, well within the pluggable's maximum power profile of 32W.
The power consumption of the AC-100 CFP, and its main components, and the target power consumptions of the components needed for a digital CFP2. Source: Gazettabyte
The start-up says it is shipping samples of the AC-100 CFP and already has 15 customers. "That includes some of the bigger [systems] players that have their own internal DSP," says Raj Shanmugaraj, CEO of Acacia. "The coherent CFP is not their focus; they are going after long-haul."
The start-up is shipping samples of the AC-100 CFP and already has 15 customers
Acacia chose to develop it own DSP chips as it sees the technology as core for coherent-based optical transmission. "That is where we see the big market," says Shanmugaraj. "We have a 100 Gig [MSA] that has been shipping, and a 200-400 Gig product that is in development."
DSP-ASIC and silicon photonics
The DSP-ASIC for the AC-100 CFP is Acacia's second chip design. Its first, a DSP-ASIC for its long-haul 5x7-inch OIF MSA transponder, is implemented using a 40nm CMOS process. The latest metro DSP-ASIC uses 28nm CMOS.
The DSP-ASIC includes analogue-to-digital (A/D) and digital-to-analogue (D/A) converters and a serialiser/ deserialiser (Serdes). Also on-chip is the digital signal processor (DSP) that implements soft-decision, forward error correction (SD-FEC) and compensation algorithms for chromatic and polarisation-mode dispersion.
Other DSP-ASIC features include spectral shaping for flexible grid transmission. "The signal processing on the transmit side fits in the one ASIC," says Benny Mikkelsen, CTO at Acacia. Also on-chip are a 100 Gig OTN (Optical Transport Network) framer and a microprocessor to manage the DSP-ASIC and the overall CFP.
The DSP-ASIC consumes 12-14W: the A/D, D/A converters and Serdes consume 5W, while the DSP consumes 7W for an 80km link - the 100 Gig equivalent of the -ZR spec - and 9W for 1,200km transmission due to the more powerful SD-FEC needed.
Mikkelsen says achieving a low-power ASIC requires several approaches. The SD-FEC is designed to be extremely low power, he says, as is the dispersion compensation: "Not just the algorithms but how we code the algorithms." Also, how the ASIC's circuitry is laid out impacts power consumption.
Acacia's engineers have also developed a silicon-photonics chip that combines the coherent transmitter and receiver optics. "The PIC [photonic integrated circuit] is the first silicon-photonics chip targeted at metro/ metro-regional," says Shanmugaraj. "It is an IC that has all the components except the laser, and is co-packaged in a gold box with the drivers and trans-impedance amplifiers."
Acacia's PIC is monolithic; all the functional blocks are implemented in silicon rather than combined silicon and III-V materials, a technique known as heterogeneous integration.
Using silicon photonics rather than indium phosphide has advantages, says Shanmugaraj. Silicon photonics benefits from mature CMOS processes developed for the semiconductor industry: "With the large silicon wafers, you can have thousands of these silicon PICs on them," he says.
Acacia tests the PICs directly on the wafer. This avoids having to dice the wafer and package each die before testing. "We also don't need thermal control [of the chip] or hermetic packaging," says Shanmugaraj. With indium phosphide, the modulators do require thermal cooling, adding to the design complexity and the power consumption. The PIC is 10mm long and consumes less than 5W.
The AC-100 CFP is expected to cost less than half the 5x7-inch 100 Gig coherent MSA which sells for $20,000. "One of the biggest pain points in metro is cost, if you ask most of the service providers," says Shanmugaraj. At below $10,000, the coherent CFP will be cost-competitive with the 100 Gig direct-detection CFP that uses 4x25 Gig wavelengths. However, the 100 Gig direct-detection CFP continues to come down in price as more products come to market.
Roadmap
Acacia will continue to address long-haul and metro, each requiring its own ASIC. "We don't believe that you can have one ASIC that serves both submarine and the metro," says Mikkelsen. In turn, silicon photonics will be used for pluggables while discrete optics will be used for the more demanding submarine.
The company says it is developing a multi-core ASIC to support super-channels and 16-QAM modulation for 200 Gig and 400 Gig transmission. The company says it will provide more details of its flexible, adaptive-rate ASIC at ECOC, to be held in September this year.
The company's product roadmap also features a co-packaged DSP-ASIC and PIC that will fit within a CFP2. Achieving such a pluggable, dubbed a digital CFP2, require a further halving of the DSP-ASIC's power consumption. This, says Acacia, is achievable using the next CMOS process node after 28nm.
The advantages of a digital CFP2 compared to a CFP2 with optics only, with the DSP-ASIC on the line card, include using the DSP-ASIC only when it is needed. When a fault occurs, the relevant pluggable can be replaced rather than having to remove the complete line card. Lastly, new functionality in the DSP-ASIC can be introduced by plugging in the new CFP2 pluggable compared with having to redesign the line card.
See also:
Transmode adopts 100 Gigabit coherent CFPs, click here
ClariPhy samples a 200 Gigabit coherent DSP-ASIC, click here